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ADE7854/ADE7858/ADE7868/ADE7878
Data Sheet
Address
0xE519
0xE51A
0xE51B
Register
Name
AVA
BVA
CVA
R/W 1
R
R
R
Bit
Length
24
24
24
Bit Length
During
Communication 2
32 SE
32 SE
32 SE
Type 3
S
S
S
Default
Value 4
N/A
N/A
N/A
Description
Instantaneous value of Phase A
apparent power.
Instantaneous value of Phase B
apparent power.
Instantaneous value of Phase C
apparent power.
0xE51F
0xE520
CHECKSUM
VNOM
R
R/W
32
24
32
32 ZP
U
S
0x33666787
0x000000
Checksum verification. See the
Checksum Register section for details.
Nominal phase voltage rms used in the
alternative computation of the
apparent power. When the VNOMxEN
bit is set, the applied voltage input in
the corresponding phase is ignored
and all corresponding rms voltage
instances are replaced by the value in
the VNOM register.
0xE521 to
0xE52E
Reserved
These addresses should not be written
for proper operation.
0xE600
0xE601
0xE602
PHSTATUS
ANGLE0
ANGLE1
R
R
R
16
16
16
16
16
16
U
U
U
N/A
N/A
N/A
Phase peak register. See Table 41.
Time Delay 0. See the Time Interval
Between Phases section for details.
Time Delay 1. See the Time Interval
Between Phases section for details.
0xE603
ANGLE2
R
16
16
U
N/A
Time Delay 2. See the Time Interval
Between Phases section for details.
0xE604 to
0xE606
Reserved
These addresses should not be written
for proper operation.
0xE607
0xE608
PERIOD
PHNOLOAD
R
R
16
16
16
16
U
U
N/A
N/A
Network line period.
Phase no load register. See Table 42.
0xE609 to
0xE60B
Reserved
These addresses should not be written
for proper operation.
0xE60C
0xE60D
0xE60E
0xE60F
0xE610
0xE611
0xE612
0xE613
0xE614
LINECYC
ZXTOUT
COMPMODE
Gain
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
16
16
16
16
16
16
16
10
16
16
16
16
16
16
16
16
16 ZP
U
U
U
U
U
U
U
U
S
0xFFFF
0xFFFF
0x01FF
0x0000
0x0E88
0x0000
0x0000
0x0000
0x0000
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation-mode register. See
Table 43.
PGA gains at ADC inputs. See Table 44.
CFx configuration register. See Table 45.
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A. See
Table 46.
0xE615
0xE616
0xE617
0xE618
0xE700
BPHCAL
CPHCAL
PHSIGN
CONFIG
MMODE
R/W
R/W
R
R/W
R/W
10
10
16
16
8
16 ZP
16 ZP
16
16
8
S
S
U
U
U
0x0000
0x0000
N/A
0x0000
0x1C
Phase calibration of Phase B. See Table 46.
Phase calibration of Phase C. See Table 46.
Power sign register. See Table 47.
ADE7878 configuration register. See
Table 48.
Measurement mode register.
See Table 49.
0xE701
0xE702
0xE703
0xE704
ACCMODE
LCYCMODE
PEAKCYC
SAGCYC
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
U
U
U
U
0x00
0x78
0x00
0x00
Accumulation mode register.
See Table 50.
Line accumulation mode behavior. See
Table 52.
Peak detection half line cycles.
SAG detection half line cycles.
Rev. H | Page 84 of 100
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